Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS

作者：Cho S H^*; Lee H D; Kim K D; Ryu S T; Kwon J K

来源：Electronics Letters, 2010, 46(5): 335-U4853.

DOI：10.1049/el.2010.3553

A new topology in PLL architecture dual-mode K(VCO) (DMK) to reduce in-band noise and reference spurs is presented. The DMK PLL also adopts the technique to shrink the spurs by modulating the control voltage. The prototype DMK PLL is implemented in a 65 nm CMOS and shows about 3 ps RMS jitter, phase noise of -107 and -109 dBc/Hz at 100 kHz, 1 MHz offset frequency and reference spur of 68.5 dBc.

• 出版日期2010-3-4