A 0.03 mm(2) delta-sigma modulator with cascaded-inverter amplifier

作者：Wang Zhidong; Duan Quanzhen; Roh Jeongjin^*

来源：Analog Integrated Circuits and Signal Processing, 2014, 81(2): 495-501.

DOI：10.1007/s10470-014-0408-8

• Delta-sigma modulator
• Analog-to-digital convertor
• Switched-capacitor circuit
• OTA

A single stage inverter is introduced as a replacement for the conventional OTA to implement an inverter-based delta-sigma modulator. It achieves a high power and area efficiency. However, the low DC-gain and gain-bandwidth (GBW) have limited the application. This paper proposes a cascaded-inverter to increase the DC-gain and GBW, while maintaining the advantages of power and area efficiency. By cascading three inverters, the DC-gain is increased from 44 dB to 82 dB, and the GBW is increased from 100 MHz to 697 MHz. A third-order delta-sigma modulator using the proposed cascaded-inverter has been fabricated in a 0.11-mu m CMOS process. When operating from a 1.2-V supply and clocked at 80 MHz, the prototype modulator achieves 59.4-dB peak SNDR over 500-kHz signal bandwidth while consuming 249 mu W. Measurement results demonstrate that the application of the inverter-based amplifier, which is becoming popular due to its high power efficiency, can be extended to significantly higher speed circuits.

• 出版日期2014-11