A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars

作者：Ng Herman Jalli^*; Fischer Alexander; Feger Reinhard; Stuhlberger Rainer; Maurer Linus; Stelzer Andreas

来源：IEEE Transactions on Circuits and Systems I-Regular Papers, 2013, 60(12): 3289-3302.

DOI：10.1109/TCSI.2013.2265966

• Delay-locked loop
• frequency multiplier
• frequency synthesizer
• frequency-modulated continuous wave radar
• linearity
• phase noise
• phase-locked loop
• 77-GHz radar
• voltage-controlled delay line
• voltage-controlled oscillator

This paper describes a frequency synthesizer for frequency-modulated continuous wave (FMCW) radars, operating in combination with a frequency multiplier, at 77 GHz. The fractional-N phase-locked loop (PLL)-based synthesizer is equipped with a wideband voltage-controlled oscillator, which is realized with CMOS transistors in a current-reuse technique, and a delay-locked loop (DLL). Utilized as a frequency multiplier for the reference signal, the DLL improves both the phase noise performance of the PLL and the linearity of the frequency sweep generated by the PLL. Two types of voltage-controlled delay lines used in the DLL are also introduced and compared in this paper. Both show a good performance in terms of phase noise and can be easily realized in a standard CMOS technology. The false-lock issue of the DLL is also discussed and a solution is proposed. Furthermore, a frequency multiplier is used to multiply the output frequency of the PLL by a multiplication factor of 18. This architecture enables an increase in the target resolution and an improvement in the accuracy of the measurements of FMCW radars.

• 出版日期2013-12