A novel lambda negative-resistance transistor in the 0.5 mu m standard CMOS process

作者：Chen Yan; Mao LuHong; Guo WeiLian; Yu Xin; Zhang ShiLin; Xie Sheng

来源：Chinese Science Bulletin, 2012, 57(7): 716-718.

DOI：10.1007/s11434-011-4900-6

• lambda negative-resistance transistor
• CMOS
• p-base layer
• peak-to-valley current ratio
• low power consumption

A novel negative-resistance transistor (NRT) with a Lambda shaped I-V characteristic is demonstrated in the 0.5 mu m standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET';s substrate. The NRT has a low valley current of -6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is -24.49 mu A which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 k Omega. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.

• 出版日期2012-3
• 单位天津大学