摘要

This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240-mV(PP), 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.

  • 出版日期2014-1