A wide range delay locked loop for low power and low jitter applications

作者：Estebsari Motahhareh; Gholami Mohammad^*; Ghahramanpour Mohammad Javad

来源：International Journal of Circuit Theory and Applications, 2018, 46(3): 401-414.

DOI：10.1002/cta.2401

• charge pump
• delay locked loop
• frequency range
• jitter
• voltage controlled delay line

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18-m CMOS technology, has a wide frequency range from 217 to 800MHz. It consumes maximum 3.4-mW and minimum 2.6-mW power dissipation in source voltage of 1.8V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217MHz and at most 25 clock cycles at 800MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65ps at 800MHz and 2.54ps at 217MHz. Moreover, its maximum peak-to-peak jitter is equal to 5.17ps, and its minimum peak-to-peak jitter is equal to 1.39ps at 217 and 800MHz, respectively.

• 出版日期2018-3