A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI

作者：Mohammadi Babak^*; Andersson Oskar; Nguyen Joseph; Ciampolini Lorenzo; Cathelin Andreia; Rodrigues Joachim Neves

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65(4): 1257-1268.

DOI：10.1109/TCSI.2017.2750762

• ULV SRAM
• 7T bitcell
• tree decoder
• single cycle boost

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28-nm FD-SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost generation unit is minimized by 66 low-power and area efficient ON-chip charge pumps, i.e., 64 for boosting the voltages on write-bitlines and two for the wordlines. The charge pump energy overhead is reduced by introducing a new boost paradigm with an on-demand activation mechanism that generates the required boost level in a single clock cycle. A sense amplifier-less read architecture enables a reliable and high performance read operation. Measurements identify several meritorious metrics. The minimum read energy is identified as 8.4 fJ/bit-access, achieved for 90-MHz operation at 0.3V. Furthermore, the minimum operating voltage is measured as 240mV, and data is retained in ultra-low voltage regime, ranging down to 0.2V. The bitcell area, implemented using standard design rules, is 0.261 mu m(2). The entire memory, including the digital test circuitry, occupies 0.161 mm(2) of chip area.

• 出版日期2018-4