A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology

作者：Lee I Ting^*; Tsai Yun Ta; Liu Shen Iuan

来源：IEEE Journal of Solid-State Circuits, 2012, 47(11): 2693-2700.

DOI：10.1109/JSSC.2012.2209810

• Leakage current
• leakage tracking
• leakage-current recycling
• low power
• MOS capacitor
• phase-locked loops

A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider, and a dual-mode phase-frequency detector. This PLL is fabricated in a 65 nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640 MHz are 52.2 ps and 9.6 ps, respectively. Its power consumption is 1.2 mW for a 1.2 V supply voltage.

• 出版日期2012-11
• 单位中国科学院电工研究所