An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity

作者:Furuta Jun*; Kobayashi Kazutoshi; Onodera Hidetoshi
来源:IEICE - Transactions on Electronics, 2010, E93C(3): 340-346.
DOI:10.1587/transele.E93.C.340

摘要

According to the process scaling, semiconductor devices are becoming more sensitive to soft errors since amount of critical charges are decreasing In this paper. we propose an area/delay efficient dual modular flip-flop, which is tolerant to SEE (Single Event Upset) and SET (Single Event Transient) It is based on a "BISER" (Built-in Soft Error Resilience) The original BISER FF achieves small area but it is vulnerable to an SET pulse on C-elements The proposed dual modular FF doubles C-elements and weak keepers between master and slave latches, which enhances SET immunity considerably with paying small area-delay product than the conventional delayed TMR FFs

  • 出版日期2010-3