A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

作者：Reviriego Pedro^*; Demirci Mustafa^*; Evans Adrian^*; Antonio Maestro Juan

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(2): 171-175.

DOI：10.1109/TCSII.2015.2483362

• Error correction codes
• high-speed networking
• memory
• single error correction (SEC)

Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protect both the data and the associated control bits. It is attractive for these codes to provide fast decoding of the control bits, as these are used to determine the processing of the data and are commonly on the critical timing path. In this brief, a method to extend SEC codes to support a few additional control bits is presented. The derived codes support fast decoding of the additional control bits and are therefore suitable for networking applications.

• 出版日期2016-2