科研之友
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摘要
We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 mu m SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.
- 出版日期2012-6
