A pipelined architecture for normal I/O order FFT

作者：Liu, Xue; Yu, Feng^*; Wang, Ze-ke

来源：Journal of Zhejiang University-Science C(Computers and Electronics), 2011, 12(1): 76-82.

DOI：10.1631/jzus.C1000234

• Fast Fourier transform (FFT)
• Single-path delay commutator (SDC)
• Pipelined FFT
• Bit reverser

We present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.

• 出版日期2011-1
• 单位浙江大学