摘要

A low-noise phasemodulator,using finite-impulse-response (FIR) filtering embedded delta-sigma (Delta Sigma) fractional-N phase-locked loop (PLL), is fabricated in 0.18.mu m CMOS for GSM/EDGE polar transmitters. A simplified digital compensation filter with inverse-FIR and -PLL features is proposed to trade off the transmitter noise and linearity. Experimental results show that the presented architecture performs RF phase modulation well with 20mW power dissipation from 1.6V supply and achieves the root-meansquare (rms) and peak phase errors of 4 degrees and 8.5 degrees, respectively. The measured and simulated phase noises of -104 dBc/Hz and -120dBc/Hz at 400-kHz offset from 1.8-GHz carrier frequency are observed, respectively.

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