A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

作者：Chen Hu; Lu Bo; Shao Ke; Xia Lingli; Huang Yumei; Hong Zhiliang^*

来源：Chinese Journal of Semiconductors, 2010, 31(1).

DOI：10.1088/1674-4926/31/1/015001

• Charge pump
• CMOS technology
• Digital frequency dividers
• Dynamic matching
• Dynamic phase
• Frequency offsets
• High-speed
• In-band noise
• In-band phase noise
• Low jitters
• PLL
• Reference spur
• Second orders
• Switch signals

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and-114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.

• 出版日期2010
• 单位复旦大学