A Micro-Power Two-Step Incremental Analog-to-Digital Converter

作者：Chen Chia Hung^*; Zhang Yi; He Tao; Chiang Patrick Y; Temes Gabor C

来源：IEEE Journal of Solid-State Circuits, 2015, 50(8): 1796-1808.

DOI：10.1109/JSSC.2015.2413842

• Analog-to-digital converter (ADC)
• chopper stabilization
• decimation filter
• delta sigma (Delta Sigma)
• extended-counting
• flicker noise elimination
• incremental data converters
• low power
• measurement and instrumentation
• multi-stage noise shaping (MASH)
• multi-step
• sensor interface
• time-domain signal processing
• two step

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an th-order IADC close to that of a (2N - 1 )th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V-PP and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm(2), and it consumes only 10.7 mu W. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

• 出版日期2015-8