A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

作者：Zhu, Zhangming^*; Wu, Hongbing; Yu, Guangwen; Li, Yanhong; Liu, Lianxi; Yang, Yintang

来源：Journal of Circuits, Systems, and Computers, 2013, 22(4): 1350018.

DOI：10.1142/S0218126613500187

• Low offset
• offset cancellation techniques
• dynamic comparator

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 mu m 3.3V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 mu W.

• 出版日期2013-4
• 单位西安电子科技大学