摘要

A physical-based analytical series resistance (R-s) model is first proposed to accurately evaluate the R-s of polycrystalline silicon thin-film transistors (TFTs). Through carefully analyzing the gate-to-source/drain overlap regions, three underlying physical effects wherein are adequately included, namely the gate (V-g)-induced carrier accumulation, current path spreading, and carrier transport via thermionic emission over grain boundaries. The proposed model can precisely reproduce the V-g dependent R-s behavior and fit the experimental data of both metal-induced lateral crystallized and excimer laser annealed TFTs. Furthermore, an explicit analytical expression of R-s is derived using appropriate approximation, based on which all underlying R-s components and their dependencies on device parameters can be clarified. Finally, feasible approaches of R-s reduction are suggested.

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