A 75-mu W, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

作者：Karkare Vaibhav^*; Gibson Sarah; Markovic Dejan

来源：IEEE Journal of Solid-State Circuits, 2013, 48(9): 2230-2238.

DOI：10.1109/JSSC.2013.2264616

• Algorithms
• architecture
• biomedical signal processing
• clustering
• digital integrated circuits
• nervous system

Energy-efficient spike-sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip spike sorting. However, previous spike-sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel spike-sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-V-T register banks. The 16-channel spike-sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 mu W at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240x reduction in the output data rate, which is 3x higher than the data-rate reduction obtained from previous spike-sorting DSP chips.

• 出版日期2013-9