A 0.18-mu m CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration

作者：Chen Yang Wen^*; Yu Yueh Hua; Chen Yi Jan Emery

来源：IEEE Microwave and Wireless Components Letters, 2013, 23(10): 551-553.

DOI：10.1109/LMWC.2013.2279113

• Charge-pump (CP) current calibration
• frequency synthesizer
• phase-locked loop (PLL)
• spur suppression

This letter presents a 0.18 mu m CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than -63 dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18-5.32 GHz and 5.74-5.82 GHz.

• 出版日期2013-10
• 单位中国科学院电工研究所