A calibration technique based on sub-stages%26apos; weights of pipelined ADC

作者：Jia Huayu; Lv Yuxiang

来源：Analog Integrated Circuits and Signal Processing, 2016, 89(1): 223-229.

DOI：10.1007/s10470-016-0818-x

• Analog-to-digital converter
• Amplifier
• Digital calibration
• Background calibration
• Finite state machines

This paper describes an efficient background calibration technique for pipelined analog-to-digital converters (ADCs). This technique calibrate the interstage gain errors, capacitor mismatches and finite opamp open-loop gain by updating the weights of sub-stages that carry the information about these errors. A weight-based errors model is built to simplify calibration algorithm. The errors are merged into the weight of the corresponding stage. The first seven stages of every signal path are calibrated to achieve high resolution and eliminate errors. Two extra sub-stages are used in the calibration process to implement background calibration. The improved technique is used in a 14-bits 80 MS/s pipelined ADC. The results demonstrate that it can decrease errors, increase the effective number of bits by 2.04, and SFDR is 90.12 dB and ENOB is 13.2 bits. The ADC implemented in chartered 0.18 mu m CMOS process consumes 260 mW, occupying a chip area of 7.16 mm(2).

• 出版日期2016-10
• 单位太原理工大学