A threshold control technique for CMOS comparator design

作者：Sun Guoquan; Zhang Yin; He Lenian; Zhu Xiaolei

来源：2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014, 2014-06-18 to 2014-06-20.

DOI：10.1109/EDSSC.2014.7061169

• Clock frequency
• CMOS comparators
• High linearity
• pMOS capacitor
• Power efficiency
• Power supply
• Threshold control
• Threshold levels

Area and power efficiency of ADC can benefit from the threshold configurable comparator based SAR ADC architecture. This work proposes a threshold control technique for CMOS comparator design with high linearity. One pair of binary weighted pMOS capacitor arrays is used to generate the built-in threshold levels;another pair of digitally switched pMOS capacitor arrays is implemented to compensate the nonlinearity for the generated threshold levels. The simulation results show the range of the controlled threshold is 260mV. 6-bit resolution with 0.6 LSB INL and 0.25 LSB DNL are achieved. The comparator consumes 5.0μW with 30MHz clock frequency from 1.8V power supply.

• 出版日期2014
• 单位浙江大学