A reconfigurable platform for evaluating the performance of QoS networks

作者：Claver J M^*; Agusti P; Arevalillo Herraez M; Leon G; Canseco M

来源：Journal of Systems Architecture, 2010, 56(4-6): 191-207.

DOI：10.1016/j.sysarc.2010.03.004

• Computer networks
• Quality of Service
• FPGA
• Handel-C
• Performance evaluation

Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components.
In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single PGA device. Hence, it can be used at design to produce more efficient devices. To illustrate the applicability of the platform we have used the Simple Multimedia Router (SMMR), an existing proposal to provide QoS.
The modular structure of the tool and the fact that it has been implemented on an PGA using a high level hardware programming language makes it flexible, scalable and easy to reconfigure. Besides, the architecture and implementation can be adapted to be used in more recent QoS NoC environments.

• 出版日期2010-6