摘要

This paper proposes a fully differential 10-bit energy efficient successive approximation register (SAR) analog-to-digital converter (ADC) by using incremental converting method. The voltage difference of the input between two successive samples is acquired and resolved. A judge window is properly designed, and several conversion steps of significant bits could be skipped when the voltage difference is within the preset Thus, the power consumptions of the digital-to-analog converter (DAC), logic circuit, and comparator are greatly saved. Moreover, the differential structure also helps to suppress common mode noise and even harmonic noise. The design is implemented with a standard 0.18-mu m CMOS technology. Test results show that the power consumption of the ADC with the proposed algorithm is reduced by at least 42.8% comparing to the conventional structure. The measured DNL and INL are within 0.29 LSB and 0.80 LSB, respectively. At a 0.6-V supply and a 200-kS/s sampling rate, the ADC achieves an ENOB of 9.34 and a figure-of-merit of 8.87 fJ/conv.-step.