An output code offset-free comparator for SAR ADCs based on non-linear preamplifier and CMOS inverters

作者：Yue Xicai^*; Krapp H G; Drakakis E M

来源：Microelectronics Journal, 2013, 44(5): 414-420.

DOI：10.1016/j.mejo.2013.02.011

• Successive approximation registers (SAR)
• ADC
• Comparator
• Non-linear amplifier
• Operating transconductance amplifier (OTA)
• CMOS invertor

The Tanh transfer function of the differential pair operating in weak inversion is employed to implement the non-linear pre-amplification for the comparator of the SAR ADC. This non-linear preamplifier achieves a low gain for large input signals therefore the comparator can operate at a full speed (overdrive-free), while the high gain it achieved for small input signals improves the accuracy of the comparator. By combining the non-linear preamplifier and CMOS inverters, the issue of the comparison point shift in CMOS inverter due to fabrication process can be neglected, providing an output code offset-free solution. Simulations for the most critical zero-crossing overdrive cases for a 12-bit SAR ADC demonstrated that by cascading four stage differential pairs, the gain difference between the input signals of (1/2)LSB and (1/4)V-ref is 49 dB, while the output of the preamplifier for the input of (1/2)LSB is big enough to tackle the comparison point shift in the following comparison stage. Fabricated using the 0.35 mu m AMS CMOS technology, the comparator occupied an area of 130 x 140 mu m(2) while consuming 6.2 mu W of power under a 1.5 V single power supply which is suitable for low-power applications. Chip tests demonstrated that the fabricated chips achieved 12-bit resolution without offset when working at 100 KSPS. This pure analog comparator could lead to higher resolution or higher speed by cascading more stages of the non-linear pair or by applying more current in the last stage of the non-linear pair.

• 出版日期2013-5