摘要

A decoding scheme of the orthogonally concatenated codes with low resource utilizations is proposed. In the optical transport networks (OTN), forward error-correction (FEC) techniques are used to reduce the errors which occur in transmissions. Two-orthogonal-concatenated (TOC) codes are widely used in FEC techniques for their powerful error-correction capabilities based on the iterative decoding procedure. However, the framing structure is complex so the decoding procedure is more difficult than the decoding of in-out concatenated codes. And the powerful error-correction capability relies on the multi-iterative decoding processing, thus how to effectively utilize the hardware resources is a very important problem. Especially when the decoding procedure is implemented in the field programmable gate array (FPGA) devices, effective optimizations are required for the limited resources. In this paper we present an iterative decoding scheme in FPGA with low resource utilizations. As an example, an actual engineering application under the G.975.1 recommendation is given to show the efficiency of the proposed design.