Digital-to-Time Converter with 3.93 ps Resolution Implemented on FPGA Chips

作者：Zhang, Min; Wang, Hai^*; Liu, Yan

来源：IEEE Access, 2017, 5: 6842-6848.

DOI：10.1109/ACCESS.2017.2700055

• Digital-to-time converter (DTC)
• quantified phase shift resolution (QPSR)
• phase difference
• field programmable gate arrays (FPGA)
• phase lock loop (PLL)

In this paper, a digital-to-time converter (DTC) based on the principle of quantified phase shift resolution (QPSR) is proposed and tested. The QPSR principle is realized by analyzing the phase relationship between two periodic signals, which distinguishes the proposed DTC from conventional DTCs. For performance evaluation, the proposed DTC is implemented on Xilinx Virtex-5 and Virtex-6 field programmable gate array (FPGA) chip, respectively. The obtained resolution of the DTC implemented on Virtex-5 FPGA is 27.1 ps, and the differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.269 degrees C 0.247 least significant bit (LSB) and 0.387 degrees C 0.171 LSB. Meanwhile, the DTC implemented on Virtex-6 FPGA can achieve a resolution of 3.93 ps, a dynamic range of 43 s, a DNL of 0.327 degrees C 0.358 LSB, and an INL of 2.6093 degrees C 2.4754 LSB. Experimental results prove that the proposed DTC features high-accuracy, low-cost, and easy implementation.

• 出版日期2017
• 单位西安电子科技大学