ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

作者：Saha P; Banerjee A; Dandapat A; Bhattacharyya P^*

来源：MICROELECTRONICS JOURNAL, 2011, 42(12): 1343-1352.

DOI：10.1016/j.mejo.2011.09.001

• Vedic multiplier
• Incrementer
• Zero detectors
• Decrementer
• Factorial design
• High speed

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like 'Urdhva-tiryakbyham' (UT) and 'Nikhilam Navatascaramam Dasatah' (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90 nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only similar to 42.13 ns while the power consumption of the same was similar to 58.82 mW for a layout area of similar to 6 mm(2). Improvement in speed was found to be similar to 33% and similar to 24% while corresponding reduction of power consumption in similar to 34.48% and similar to 24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.

• 出版日期2011-12