A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet

作者：Wu Ke Chung^*; Lee Jri

来源：IEEE Journal of Solid-State Circuits, 2010, 45(11): 2421-2432.

DOI：10.1109/JSSC.2010.2074291

• 100 GbE
• bandgap reference
• bit error rate (BER)
• clock and data recovery (CDR)
• clock multiplication unit (CMU)
• demultiplexer (DMUX)
• deskew circuit
• divider
• jitter tolerance
• limiting amplifier (LA)

A 2x25-Gb/s receiver for 100-Gb Ethernet (100 GbE) has been implemented in 65-nm CMOS technology. A new regulation mechanism is applied to the limiting amplifier to minimize its gain and bandwidth variations. Two low-power full-rate CDRs (with a built-in clock generator) and a high-speed 2:5 DMUX circuit are integrated. Although only two channels are implemented, this receiver provides exactly the same operation as a four-channel one while dealing with independent channels. The prototype achieves bit error rate <10(-12) with 20-mV(pp) input sensitivity, consuming a total power of 510 mW from a 1.2-V supply.

• 出版日期2010-11
• 单位中国科学院电工研究所