科研之友
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摘要
Chip-to-wafer stacking is a key enabling technology for two and half dimension (2.5D) as well as for three dimension (3D), with technological challenges driven by the increase of the die surface and the number of input/outputs (I/Os) and the reduction of the vertical dimensions. In our investigation, chips were assembled using a back-to-face approach on a silicon interposer containing copper through-silicon vias (TSVs). This technology is based on the realization of a high-topology redistribution layer passing over the dies bonded with the active face up on the interposer by using a polymer layer. This architecture is attractive because of the reduction of the chip thickness to an ultrathin dimension, and can offer substantial advantages in terms of design flexibility and technology cost. In this architecture, chip bonding strategies are compared: several bonding materials were tested either on the die side using die-attach film or on the bottom side of the interposer using wafer-level spin-coated polymers. Then, a novel brick (sequence) of processes consisting of high-topology encapsulation and metallization was fully developed to connect the top dies to the bottom wafer. The resulting structure has been modeled through the temperature cycles seen during fabrication using a thermomechanical finite element modeling (FEM) simulation for different geometries and materials. The results indicate a moderate level of stress in the stacked film layers with some concentration in localized regions of the topology. Electrical tests have also been completed at the wafer level, showing low resistances and high yield at front-side and at the back-side level after TSV exposure. Successful reliability tests have also been carried out and support the good mechanical behavior of this integration.
- 出版日期2014-3
- 单位中国地震局
