An 18-Gb/s Fully Integrated Optical Receiver With Adaptive Cascaded Equalizer

作者：Pan, Quan^*; Wang, Yipeng; Lu, Yan; Yue, C. Patrick

来源：IEEE Journal of Selected Topics in Quantum Electronics, 2016, 22(6): 6100509.

DOI：10.1109/JSTQE.2016.2574567

• Optoelectronic integrated circuits
• optical receivers
• silicon photodetector
• inverter-based cascode transimpedance amplifier
• low dropout regulator
• DC offset cancellation
• continuous-time linear equalizer (CTLE)
• adaptive equalizer
• limiting amplifier (LA)

An 18-Gb/s fully integrated optoelectronic integrated circuit for short-distance communications is realized in the TSMC 65-nm CMOS process. The system consists of a CMOS on-chip photodetector, an inverter-based cascode transimpedance amplifier, a DC offset cancellation buffer, a main amplifier, a three-stage tunable continuous-time linear equalizer, a two-stage modified limiting amplifier, a DC offset cancellation network, an adaptive equalization loop, a low dropout regulator, and a 50-Omega termination output buffer. The CMOS P-Well/Deep N-Well on-chip photodetector improves bandwidth and responsivity without technology modification. Moreover, the adaptive cascaded equalization further compensates for the limited bandwidth of the on-chip photodetector with a 5-10-dB/dec roll-up frequency response. The electrical measurement results show a transimpedance gain of 102 dB Omega and a bandwidth of 12.5 GHz. Furthermore, the optical measurement results demonstrate a fully integrated solution with (1) standard mode: data traffic of 9 Gb/s for 2(15)-1 PRBS with 10(-12) BER, -4.2-dBm optical input sensitivity, and 5.33-pJ/b efficiency; (2) avalanche mode: data traffic of 18 Gb/s for 2(15)-1 PRBS with 10(-12) BER, -4.9-dBm optical input sensitivity, and 2.7-pJ/b efficiency. The chip occupies a core area of 0.23 mm(2) and dissipates 48 mW from a 1/1.2-V voltage supply.

• 出版日期2016-12
• 单位澳门大学; 香港科技大学