A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

作者：Cho Young Kyun^*; Jeon Young Deuk; Nam Jae Won; Kwon Jong Kee

来源：Microelectronics Journal, 2011, 42(12): 1335-1342.

DOI：10.1016/j.mejo.2011.09.006

• Successive approximation register (SAR)
• analog-to-digital converter (ADC)
• Bootstrapped switch
• Merged-capacitor switching
• Asynchronous clock
• Dynamic gate biasing

A 10-bit 30-MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low-power sub-sampling applications, is presented. Bootstrapped switches are used to enhance the sampling linearity at the high input frequency. The proposed ADC adopts a binary-weighted split-capacitor array with the energy efficient switching procedure and includes an asynchronous clock scheme to yield more power and speed-efficiency. The ADC is fabricated in a 65 nm complementary metal-oxide-semiconductor technology and occupies an active area of 0.07 mm(2). The differential and integral nonlinearities of the ADC are less than 0.82 and 1.13 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 56.60 dB, a spurious free dynamic range of 73.35 dB, and an effective number of bits (ENOB) of 9.11-bits with a 2.5-MHz sinusoidal input at 30-MS/s. It exhibits higher than 8.86 ENOB for input frequencies up to 78-MHz. The ADC consumes 0.85 mW at a 1.1 V supply and achieves a figure-of-merit of 51 fJ/conversion-step.

• 出版日期2011-12