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摘要
It is well known that common subexpression elimination techniques minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. Two classes of common subexpressions occur in the canonic signed digit representation of filter coefficients, called the horizontal and the vertical subexpressions. Previous works have not addressed the trade-offs in using these two types of subexpressions on the logic depth and the number of logic operators of coefficient multipliers. In this paper, we analyze the impact of the horizontal and the vertical common subexpression elimination techniques on reducing the logic depth and number of logic operators in FIR filters. Further, we present an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common subexpression elimination algorithms in literature. The design examples show that the average reduction of logic operators achieved using our method over the weight-2 horizontal common subexpression elimination method which produced the best trade-off between logic operators and logic depth (contention resolution algorithm, CRA-2 [F. Xu, C.-H. Chang, C.-C. Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. 1152(10) (2005) 695-700 (October)]) is 15%. This reduction of logic operators is achieved without any increase in the logic depth. When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park. FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27(5) (2008) 958-962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.
- 出版日期2010-1
- 单位南阳理工学院
