Assessment of ultra-thin Si wafer thickness in 3D wafer stacking

作者：Kim Eun Kyung^*

来源：Microelectronics Reliability, 2010, 50(2): 195-198.

DOI：10.1016/j.microrel.2009.10.002

3D integration with multi-stacked wafers is a promising option to enhance device performance and density beyond traditional device scaling limits. However, to bring wafer stacking into reality, there are many technological challenges to be resolved, and one of those is the problem of uniform Si wafer thinning. For multi-stacked devices, Si wafers must be drastically thinned down to less than 50 mu m. Problems associated with such Ultra-thin Si wafers range from basic wafer handling to difficulty in accurately assessing the thickness of the thinned wafer across the wafer. In this Study, bonded wafer pairs have been prepared with different bonding materials, and the stacks were ground down to about 30 mu m. The thickness of the ultra-thin wafers was measured by Fourier transform infrared spectrometry (FTIR) technique, and its stability based on bonding status as well as measuring issues will be discussed.

• 出版日期2010-2