A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3-mu m LTPS-TFT Technology

作者：Lin Wei Ming^*; Liu Shen Iuan; Kuo Chun Hung; Li Chun Huai; Hsieh Yao Jen; Liu Chun Ting

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2009, 56(2): 142-146.

DOI：10.1109/TCSII.2008.2011607

• Calibration
• charge pump (CP)
• low-temperature polysilicon thin-film transistor (LTPS-TFT)
• phase-locked loop (PLL)

A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3-mu m low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 mm(2), and it consumes 7.81 mW at 10.5 MHz. The measured static phase error without and with calibration is 80 and 6.56 ns, respectively, at 10.5 MHz. The measured peak-to-peak jitter without and with calibration is 3.573 and 2.834 ns, respectively. The measured reference spur is -26.04 and -30.2 dBc without and with calibration, respectively. The measured maximal locked time is 1.75 ms.

• 出版日期2009-2
• 单位中国科学院电工研究所