Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

作者：Mohanty Basant K^*; Meher Pramod Kumar

来源：IEEE Transactions on Signal Processing, 2011, 59(5): 2072-2084.

DOI：10.1109/TSP.2011.2109953

• Discrete wavelet transform (DWT)
• lifting
• systolic array
• VLSI
• 2-dimensional (2-D) DWT

In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the hardware utilization efficiency (HUE). Moreover, the proposed structure is scalable for high-throughput and area-constrained implementation. We have removed all the redundancies resulting from decimated wavelet filtering to maximize the HUE. The proposed design involves L pyramid algorithm (PA) units and one recursive pyramid algorithm (RPA) unit, where R = N/P, L = inverted right perpendicularlog(4) Pinverted left perpendicular and P is the input block size, M and N, respectively, being the height and width of the image. The entire multilevel DWT is computed by the proposed structure in M R cycles. The proposed structure has O(8R x 2(L)) cycles of output latency, which is very small compared to the latency of the existing structures. Interestingly, the proposed structure does not require any line-buffer or frame-buffer, unlike the existing folded structures which otherwise require a line-buffer of size O(N) and frame-buffer of size O(M/2 x N/2) for multilevel 2-D computation. Instead of those buffers, the proposed structure involves only local registers and RAM of size O(N). The saving of line-buffer and frame-buffer achieved by the proposed design is an important advantage, since the image size could very often be as large as 512 x 512. From the simulation results we find that, the proposed scalable structure offers better slice-delay-product (SDP) for higher throughput of implementation since the on-chip memory of this structure remains almost unchanged with input block size. It has 17% less SDP than the best of the corresponding existing structures on average, for different input-block sizes and image sizes. It involves 1.92 times more transistors, but offers 12.2 times higher throughput and consumes 52% less power per output (PPO) compared to the other, on average for different input sizes.

• 出版日期2011-5