A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications

作者：Tikekar Mehul^*; Huang Chao Tsung; Juvekar Chiraag; Sze Vivienne; Chandrakasan Anantha P

来源：IEEE Journal of Solid-State Circuits, 2014, 49(1): 61-72.

DOI：10.1109/JSSC.2013.2284362

• DRAM bandwidth reduction
• entropy decoder
• high-efficiency video coding
• inverse discrete cosine transform
• (IDCT)
• motion compensation cache
• ultrahigh definition (ultra
• HD)
• video-decoder chip.

High Efficiency Video Coding, the latest video standard, uses larger and variable-sized coding units and longer interpolation filters than H. 264/AVC to better exploit redundancy in video signals. These algorithmic techniques enable a 50% decrease in bitrate at the cost of computational complexity, external memory bandwidth, and, for ASIC implementations, on-chip SRAM of the video codec. This paper describes architectural optimizations for an HEVC video decoder chip. The chip uses a two-stage subpipelining scheme to reduce on-chip SRAM by 56 kbytes-a 32% reduction. A high-throughput read-only cache combined with DRAM-latency-aware memory mapping reduces DRAM bandwidth by 67%. The chip is built for HEVC Working Draft 4 Low Complexity configuration and occupies 1.77 mm(2) in 40-nm CMOS. It performs 4K Ultra HD 30-fps video decoding at 200 MHz while consuming 1.19 nJ/pixel of normalized system power.

• 出版日期2014-1
• 单位清华大学; MIT