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摘要
To reduce the contact resistance at source/drain regions in scaled CMOS, control of PtSi work function by alloying with Hf was investigated. Pt(10-20 nm)/Hf(0-10 nm)/n-Si(100) stacked layers were annealed at 400 degrees C/60 min in a flowing N-2 ambient to form silicide layer. In the case of alloying with 3-6 nm-thick Hf, it was found that barrier height (Phi(Bn)) for electron was linearly reduced from 0.84 eV to 0.56 eV with Hf thickness in the initial stacked layer, which corresponds to the work function of 4.89 eV and 4.61 eV, respectively. Furthermore, the reduction of Phi(Bn) could be precisely controlled by 94meV/nm with Hf thickness.
- 出版日期2011-1-10
