A Five-Stage Pipeline Architecture of the Unscented Kalman Filter for System-on-Chip Applications

作者：Soh Jeremy; Wu Xiaofeng^*

来源：IEEE Transactions on Industrial Electronics, 2018, 65(3): 2785-2794.

DOI：10.1109/TIE.2017.2740844

• Co-design
• field programmable gate array (FPGA)
• Kalman filter
• pipeline
• system-on-chip (SoC)
• state estimation
• unscented Kalman filter (UKF)

As an increasing number of mobile robotic systems with an ever greater autonomous capability are developed, there is a proportional increase in the demand for fast and accurate state estimation for those systems. For these increasingly complex systems, high performance and light, compact form factors are often opposing forces in design. In addition, there are applications where it may be appropriate to use multiple instances of the system operating in some formation/constellation, which has the potential to further increase the computational load on each individual system. A hardware approach based on a field programmable gate array may be able to miniaturize the state estimation subsystem while retaining the desired high performance but also has a more complex development process compared to traditional software-based designs. Leveraging the advantages of both approaches, a hardware/ software co-design of the unscented Kalman filter with a five-stage pipeline is presented. Simulated results of the design for a small (five) constellation of nanosatellites are presented as are implementation results (timing, synthesis, and power) on the Zynq-7000 XC7Z045 for the one, two, five, and ten processing element cases. A secondary hardwarein-loop simulation of single 3U CubeSat is also presented.

• 出版日期2018-3