摘要
A 5.2 GHz, 0.43 V voltage-controlled oscillator (VCO) is designed and implemented in a 0.18 mu m CMOS IP6M process. The designed circuit topology consists of two parallel LC resonators it? series with the gates of negative differential resistance transistors. At the supply voltage of 0.43 V, the output phase noise of the VCO is - 116d Bc/Hz at 1 MHz offset frequency front the carrier frequency of 5.3 GHz, and the figure of merit is - 1878dBc/Hz. Total VCO core power consumption is 1.83 in W. Tuning range is about 710 MHz, from 5.54 to 4.83 GHz, whereas the control voltage was tuned from 0 to 1.2 V.
- 出版日期2009-4