Multichannel Clock and Data Recovery: A Synchronous Approach

作者：Nassar Ahmed^*; Emira Ahmed; Mohieldin Ahmed Nader; Hussien Ahmed

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2010, 57(5): 329-333.

DOI：10.1109/TCSII.2010.2047308

• Data transmission
• delay lines
• phase-locked loops (PLLs)
• timing jitter

This brief proposes a scalable multichannel clock and data recovery architecture that exploits the synchrony of multiple point-to-point serial links and uses a single voltage-controlled oscillator (VCO) to drive multiple phase detection loops. The proposed architecture can be naturally reduced by design to an ensemble of weakly interacting delay-locked loops. As a result, the jitter peaking problem is asymptotically eliminated, which makes this architecture well suited for use in long-haul repeater chains. Moreover, it allows controlling VCO jitter transfer to the recovered clock without affecting data jitter transfer. The architecture is demonstrated both by a Verilog-A behavioral model along with a rigorous system and statistical analysis.

• 出版日期2010-5