Design and Evaluation of Efficient Router Architecture for Triplet-Based Network-on-Chip Topology

作者：Zhang Yang^*

来源：Journal of Testing and Evaluation, 2014, 42(6): 20130182.

DOI：10.1520/JTE20130182

• network-on-chip
• router architecture
• triplet-based topology
• performance evaluation

A network-on-chip (NoC) router serves an important function in network communication performance. A high-performance router will help build a high-throughput, power-efficient, and low-latency NoC. However, the existing baseline router of a triplet-based NoC topology cannot fully optimize the potential performance, because it does not consider the characteristics of triplet-based NoC topology. This paper presents the topology-related router architecture for a triplet-based topology, called X Router. The baseline router architecture is optimized using four measures, namely, simplified crossbar switch, express virtual channel, group-priority scheme, and shared buffer organization. Simulation results using the cycle-accurate simulator Noxim show that the X Router cannot only decrease traffic latency and energy consumption, but also improve throughput over the baseline router architecture.

• 出版日期2014-11
• 单位河北科技大学