A 2 mW, 50 dB DR, 10 MHz BW 5x Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF

作者：Lee Inhee^*; Han Gunhee; Chae Youngcheol

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62(1): 80-89.

DOI：10.1109/TCSI.2014.2347234

• Bandpass Delta Sigma modulator
• inverter-based OTA
• low power
• low voltage
• radio receiver
• switched-capacitor circuit
• time-interleaved ADC

A 2 mW 50 dB-DR 10 MHz-BW bandpass (BP) delta-sigma (Delta Sigma) modulator for a digital-IF receiver is presented. It is based on a power-efficient time-interleaved (TI) architecture, which uses a recursive loop and a feed-forward topology. To further improve its power-efficiency, the ADC employs inverter-based OTAs with the help of auxiliary inverters for extra gain. A 0.55 mm(2) chip is fabricated in a 0.18 mu m CMOS process. Measurements show that the prototype five-path TI BP Delta Sigma modulator achieves 50 dB DR and 46 dB SNDR with 10 MHz bandwidth at 50 MHz IF while dissipating only 2 mW.

• 出版日期2015-1