A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

作者：Lin Chi Sheng^*; Chien Ting Hsu; Wey Chin Long

来源：IEEE Transactions on Circuits and Systems II-Express Briefs, 2011, 58(9): 550-554.

DOI：10.1109/TCSII.2011.2161167

• Divider cell
• full modulus range
• phase-locked loop (PLL)
• power efficiency
• programmable frequency divider

Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is presented, where the supply voltage of 1.0 V is employed. The divider achieves a full modulus range from 1 to 256 and operates over a wide range maintaining up to 4 GHz with -30-dBm input power. The divider also accomplishes a power efficiency of 12.8 GHz/mW with 0.5-V supply voltage. It is favorable for advanced processes.

• 出版日期2011-9
• 单位中央民族大学