A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

作者：Elkholy Ahmed; Saxena Saurabh; Nandwana Romesh Kumar; Elshazly Amr; Hanumolu Pavan Kumar

来源：IEEE Journal of Solid-State Circuits, 2016, 51(8): 1771-1784.

DOI：10.1109/JSSC.2016.2557807

• ADPLL
• DAC
• digital PLL
• digitally controlled
• oscillator (DCO)
• DTC
• dual-path
• fractional-N
• frequency synthesizer
• jitter
• LMS
• multi-modulus divider (MMD)
• phase-locked loops (PLLs)
• ring oscillator
• TDC
• wide bandwidth

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), Delta Sigma fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit ( FoM(J)) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 ps(rms) integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than - 96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoMJ is - 228.5 dB, which is the best among all reported ring-based FNPLLs.

• 出版日期2016-8