科研之友
微信
新浪微博
Facebook
分享链接
摘要
The electrical devices in modern world tend to be miniaturized and have multi-functional performance. Therefore, many microelectronics manufacturers have been interested in the three dimensional (3D) stacked flip chip package, because of its many advantages such as smaller foot print and higher electrical and thermal performances than the conventional wire bonding method. As a number of electrical and electronic equipment manufacturers interest in increasing chip densities, 3D silicon integration technologies are emerging to support next generation high-end semiconductors. Recently, interests in ultrasonic flip chip bonding technology has been growing due to its benefits of lower cost, lower operation temperature and shorter bonding time than the conventional thermal compression bonding. In this study, the reliability of 3D stacked flip chip package bonded with non-conductive paste (NCP) using ultrasonic energy and thermal compression energy were evaluated under temperature and humidity (TH) and thermal shock (TS) tests. The printed circuit board, silicon carrier and silicon chip are integrated with two different bonding methods. The two bonding methods were carried out with NCP under optimum bonding pressure, temperature and time. The electrical resistance of the flip-chip package was measured with reliability test (TH and TS) time.
- 出版日期2017-5
