摘要
Advanced FinFETs fabricated on SiO(2)-Si(3)N(4)-SiO(2) (ONO) buried insulator are investigated for flash memory applications. Systematic measurements reveal that the Si(3)N(4) layer can easily trap charges by applying appropriate drain bias. The amount of trapped/detrapped charges in the buried nitride is sensed remotely by gate coupling through the variation of the drain current flowing at the front-gate interface. The front-channel threshold voltage variation, Delta V(THF), resulting from the charge trapping, induces a hysteresis "window" proper to non-volatile memory devices. Finally, our measurements highlight the geometrical parameter effects on the memory window size.
- 出版日期2011-7