A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs

作者：He Lin^*; Yang Jiaqi; Luo Duona; Jin Lele; Zhang Shuangshuang; Lin Fujiang; Yao Libin; Jiang Xicheng

来源：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62(1): 26-30.

DOI：10.1109/TCSII.2014.2362722

• Analog-to-digital conversion (ADC)
• asynchronous
• gain mismatch
• high speed
• offset mismatch
• successive approximation register (SAR) ADC
• successive approximation
• time interleaved (TI)

A single-channel asynchronous successive approximation register analog-to-digital converter with a dual-trial instantaneous switching scheme is presented in this brief. The proposed architecture uses two capacitive digital-to-analog converter (DAC) arrays to generate two possible outputs while the comparator is in the regeneration process. Two comparators are assigned to each DAC to alternately switch between the compare phase and the reset phase. Such an approach allows the overlapping of the DAC settling, the comparator reset, and the comparator regeneration, which significantly improves the conversion speed. Furthermore, the random nature of the internal channel selection converts the mismatches between both channels into wideband noise, which improves the spurious-free dynamic range.

• 出版日期2015-1
• 单位中国科学技术大学; 昆明物理研究所