A Design Methodology for a DPA-Resistant Circuit with RSL Techniques

作者：Suzuki Daisuke^*; Saeki Minoru; Shimizu Koichi; Satoh Akashi; Matsumoto Tsutomu

来源：IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2010, E93A(12): 2497-2508.

DOI：10.1587/transfun.E93.A.2497

• side channel attacks
• differential power analysts
• hardware countermeasure
• random switching logic
• CMOS logic circuit

A design methodology of Random Switching Logic (RSL) using CMOS standard cell libraries is proposed to counter power analysis attacks against cryptographic hardware modules The original RSL proposed in 2004 requires a unique RSL gate for random data masking and glitch suppression to prevent secret information leakage through power traces In contrast our new methodology enables to use general logic gates supported by standard cell libraries In order to evaluate its practical performance in hardware size and speed Is well as resistance against power analysis attacks an AES circuit with the RSL technique was implemented as a cryptographic LSI using 130 nm and 90 nm CMOS standard cell library From the results of attack experiments that used a million traces we confirmed that the RSL AES circuit has very high DPA and CPA resistance thanks to the contributions of both the masking function and the glitch suppressing function

• 出版日期2010-12