A million spiking-neuron integrated circuit with a scalable communication network and interface

作者：Merolla, Paul A.; Arthur, John V.; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S.; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L.; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K.; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D.; Risk, William P.; Manohar, Rajit; Modha, Dharmendra S.^*

来源：Science, 2014, 345(6197): 668-673.

DOI：10.1126/science.1254642

• ARCHITECTURE
• SYSTEM

Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.

• 出版日期2014-8-8