A Fractional-N PLL with Dual-Mode Detector and Counter

作者：Park Fitzgerald Sungkyung^*; Klemmer Nikolaus

来源：IEICE - Transactions on Electronics, 2012, E95C(12): 1887-1890.

DOI：10.1587/transele.E95.C.1887

• fractional-N PLL
• dual-mode detector
• phase frequency detector
• digital counter
• digital delta-sigma modulator

A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

• 出版日期2012-12